Friday, April 13, 2012

Source code of FPGA implementation

This file pcie360_0_1_20120413.zip contains the VHDL code for the FPGA implementation of the 2065 emulator (incomplete, but capable of some elementary operations from the console panel). Here's the description from the top-level file (pcie360.vhd):

This is the design for an FPGA implementation of an IBM 2065 CPU emulator. As I have insufficient documentation on the IBM 2065, and because I don't have a copy of the ROS contents of the 2065, this is really an IBM 7201-2 CE emulator with 7201-specific bits stripped out.

Major subcomponents are:
  • cpu - actual CPU emulation
  • blinken - interface to an IBM 2065 console panel w/shift registers
  • corememory - 256 KB of main memory (dual-ported between cpu and ioce)
  • ioce - interface for the IOCE emulator running on the PC
  • pcie - PCIE endblock to communicate with the PC (*)

This design is intended to be implemented on the Xilinx ML509 / XUPV5 developer board.

(*) A Xilinx PCI Express Endpoint Core example design needs to be added for this design to work. I cannot include that here because of copyright restrictions.

PCIe hardware design

I realised that I'd need some extra hardware to connect the PCIe card to the console panel. The I/O pins on the Xilinx board operate at either 2.8 or 3.3 volts, and my console panel circuitry operates at 5 volts. So, what I need is some level shifters. I got four of these 4-way level shifters, and put them on a piece of veroboard with connectors for the Xilinx board and a 50-pin ribbon cable.
The 50-pin ribbon cable terminates in an HD50 connector (commonly used for narrow SCSI applications) on a PCI bracket. The panel has been fitted with the same connector, so a SCSI cable can be used as an interconnect between the PC and the panel.

A new probem is that the PCIe card doesn't fit the computer case. The pc is housed in a 4U high 19" case. Even though there's a good deal of space, the Xiling card is just too tall. A few connectors and the CompactFlash card stick out.

For now, I've put the top cover on four standoffs. I just daren't put any real load (like the console typewriter) on top of it now.

I'm going to create some extra space in the top of the case by replacing the video card and cpu cooler with low-profile ones. I can then mount the Xilinx card horizontally above those components, using a flexible PCIe extender, similar to this.

Monday, April 2, 2012

Emulator goes hardware

Over the past few weeks, I've decided that there are a two things I don't like about the current 2065 emulator. These are:

  • In the real 2065, several things would happen at once every 10 ns sub-cycle. The software emulator is necessarily much more sequential;
  • The blinkenlights console doesn't get updated frequently enough.
Rather radically, I have therefore decided to change the emulator from a software emulator into a hardware emulator. Inspired by Lawrence Wilkinson's model 30 emulator on an FPGA, I'm going to implement the 2065 emulator on an FPGA as well.

The idea is to have the 2065 CPU and memory, as well as the logic to control the console panel on the FPGA board. For now, I'm not going to implement channel I/O on the FPGA, in stead, the FPGA will be interfaced with a PC running a software emulator of the channel and other I/O hardware.

The interface between the FPGA and the sioftware I/O will need to be able to support the following actions:

- The FPGA tells the software to execute an IPL, START I/O, TEST I/O, HALT I/O or TEST CHANNEL command;

- The software has read and write access to main memory implemented on the FPGA board;

- The software signals interrupt status to the FPGA board;

- The FPGA board signals interrupt completion to the FPGA board.

The interface needs to be reasonably fast and reliable. I found that FPGA development boards are available that fit into a PCIe slot. I've selected the Xilinx XUPV5 board pictured above for this project, as it has ample logic, a PCIe interface, and I/O pins that don't use exotic connectors.

Next thing to do is to build a small interface to connect the XUPV5 to the shift registers that drive the console panel.