Monday, April 2, 2012

Emulator goes hardware

Over the past few weeks, I've decided that there are a two things I don't like about the current 2065 emulator. These are:

  • In the real 2065, several things would happen at once every 10 ns sub-cycle. The software emulator is necessarily much more sequential;
  • The blinkenlights console doesn't get updated frequently enough.
Rather radically, I have therefore decided to change the emulator from a software emulator into a hardware emulator. Inspired by Lawrence Wilkinson's model 30 emulator on an FPGA, I'm going to implement the 2065 emulator on an FPGA as well.

The idea is to have the 2065 CPU and memory, as well as the logic to control the console panel on the FPGA board. For now, I'm not going to implement channel I/O on the FPGA, in stead, the FPGA will be interfaced with a PC running a software emulator of the channel and other I/O hardware.

The interface between the FPGA and the sioftware I/O will need to be able to support the following actions:

- The FPGA tells the software to execute an IPL, START I/O, TEST I/O, HALT I/O or TEST CHANNEL command;

- The software has read and write access to main memory implemented on the FPGA board;

- The software signals interrupt status to the FPGA board;

- The FPGA board signals interrupt completion to the FPGA board.

The interface needs to be reasonably fast and reliable. I found that FPGA development boards are available that fit into a PCIe slot. I've selected the Xilinx XUPV5 board pictured above for this project, as it has ample logic, a PCIe interface, and I/O pins that don't use exotic connectors.

Next thing to do is to build a small interface to connect the XUPV5 to the shift registers that drive the console panel.


  1. Hi Camiel,

    This sounds all very ambitious !
    What is the problem with the 10ns update of the console lights exacty ?

    I know that you used LEDs instead of old light bulbs. IBM used also thyristers to switch on the console lights which stayed on for the remaining duration of the 50/60 mains cycle.
    After zero crossing the light was turned off agaian.
    This way you could see a 10ns pulse on the console.


  2. Hi Camiel

    Good luck with your endeavours – if anyone can do it then you can! I shall follow your progress with great interest.

    The real 360s did I/O via memory the same way that you are proposing, so I think it is more appropriate to interface to a separate PC than to include I/O in the FPGA itself.

    In 360 models 50 and above the I/O was in a separate box (the ‘channel controller' [2060/2870]) which was called the IOCE in the 9020 – as you well know.

    As ever, if there’s anything I can do to help then don’t hesitate to ask. I have a full set of ALDs if the information would be of any use, though you will be emulating at the microcode level rather than the logic level.

    Keep us posted!


  3. I'm watching your progress and also Lawrence Wilkinson's with the long term goal to build a S/360 clone for home usage :-)

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  5. I'm afraid progress is very slow right now; I have a lot of work, and I've also got this [] pile of old DEC equipment to sort through and organize.

  6. Hi Camiel
    That's fascinating re the IBM 360! I wrote my first program on an IBM 360/50 in 1972. To recreate the masthead/topbar maybe the following could help:

    best regards

    Dublin, Ireland