Friday, April 13, 2012

Source code of FPGA implementation

This file contains the VHDL code for the FPGA implementation of the 2065 emulator (incomplete, but capable of some elementary operations from the console panel). Here's the description from the top-level file (pcie360.vhd):

This is the design for an FPGA implementation of an IBM 2065 CPU emulator. As I have insufficient documentation on the IBM 2065, and because I don't have a copy of the ROS contents of the 2065, this is really an IBM 7201-2 CE emulator with 7201-specific bits stripped out.

Major subcomponents are:
  • cpu - actual CPU emulation
  • blinken - interface to an IBM 2065 console panel w/shift registers
  • corememory - 256 KB of main memory (dual-ported between cpu and ioce)
  • ioce - interface for the IOCE emulator running on the PC
  • pcie - PCIE endblock to communicate with the PC (*)

This design is intended to be implemented on the Xilinx ML509 / XUPV5 developer board.

(*) A Xilinx PCI Express Endpoint Core example design needs to be added for this design to work. I cannot include that here because of copyright restrictions.

1 comment:

  1. I worked on these systems when they were *NEW* and have always been searching for a front panel. You mentioned in a prior post that the topbar is missing - that was the much prized posession of any senior systems programmer during an upgrade - they were always removed and ended up on someone's desk.

    Will you be enabling the roll switches to change register displays as well? That wasn't quite clear in reading the prior logs.

    Impressive work, worthy of the 360 and 370 guru's and wizards.